Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi qieda,
Thanks for your reply!
I agree with you comment on cycle to cycle jitter(Jcc).
But I read in paper that:
period jitter(Jp) is the difference between instantaneous peiod with the idea period.
accumulated jitter (Ja,also called long term jitter) is the difference between the...
Hi everybody,
I have read from paper that the relationship between RMS value of jitter and peak to peak jitter is depend on BER. Can anyone tell me what BER stand for here and why it has relationship with p-p jitter?
Hi everyone,
I the width of rising(or falling) edge in eye diagram is equal to the peak to peak value of jitter. But what type of jitter it represent for? long term jitter or period jitter?
Hi everyone,
I'm study jitter of PLL now, and I found there are cycle to cycle jitter, period jitter, accumulate jitter to discribe jitter in PLL. For PLL, can I say cycle -cycle jitter is smaller than period jitter, and period jitter is smaller than accumulate jitter?
Hi all,
I'm recently doing the jitter simulation of PLL, and I first got phase noise of PLL by adding every part of noise of PLL.
Then calculate jitter by the following formula:
phase jitter = sqrt(integral(fre,2*Lpll))/(2*pi*f);
period jitter =...
Re: Need help for pll design
Yes, I'm now using the s-domain model to compute the parameter of the pll, but when I used the designed parameter in z-domain model, the phase margin will be worsen for about 10 degree, and so I had to tune the parameter in hand, which is very troublesome. So I...
Re: Need help for pll design
I said PLL is a discrete system is because PFD/CP works like the sample system, and in the paper "Charge-Pump Phase-Lock Loops" writen by Gardner, it said that
"A continuous-time approximation is not valid if the loop bandwidth approaches the input frequency. In...
Re: Need help for pll design
Because PLL is a discrete system, in the case the fref=6fu, the s-domain model will deviate from the real situation, and I think z-model will be more suitable.
pll design
Hi,
every one.
I'm now designing a pll with reference clock frequency only 6 times to the bandwidth of the pll loop, and in this case the s-domain model is no longer suitable, and z-domain model must be used to model the pll loop. So in this case, I don't know how to design pll...
hi everybody,
I have design an AGC based on 3 stage linear dB VGA and peak detector,LPF. and there is DC offset cancel block in the VGA circuit, which is made of a low pass path from the VGA output feedback to the VGA input, so that there will be a zero(about 500Hz) and a pole(about 10khz)...
Yes, if the LPF is a integrator(1/st), then the the comparator can be a purely subtractor(how to design this subtractor?). But if the LPF is not a integrator, such as 1/(1+st), then the comparator should have relative large gain.
I have analysed the loop, and found it only has one left...
My AGC is consist of VGA(exponent function), peak detector, comparator (to make the peak of output signal be equal to Vref), LPF. So which parameter will affect the stability of the AGC loop, It seems to be that only the dynamic of VGA, the time to detect the peak of the output signal, time...
Thank you for your reply,
I have read the first paper you uploaded, but this paper focus on the settling time of the AGC, and I also don't know how to make the AGC stable.
From the first paper you uploaded it seem to be that the AGC will be stable if an exponent VGA is used , and the time...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
