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Leakage is a physical feature of small geometris
You can not do anything about it on design level, You have to change
type of transistors to for instance HighVt transistors
or turn that part off, i.e. no VDD => no leakage
/Konrad
Re: CVS and HDL code
I would say CVS is perfect for HDL designs no matter, if you are alone or working on a multi-site project.
I also use it for, having both Linux and Windows source trees in sync
/Konrad
Chipscope is really easy to use!
Install and generate (use generate from menu) the ILA's you need instantiate in HDL code
After map place and route, download to FPGA and use chipscope analyzer and JTAG cable to connect
Works perfect
Best reagrds Konrad
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