Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello.
I am trying to do something similar to hard macro or hierarchical synthesis.
Here, I have UnitA. I finished synthesis and PnR for this UnitA block. So, I now have FRAM, netlist verilog, sdf etc. about this block UnitA.
Now I am trying to synthesize and PnR for UnitB. UnitB is composed...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.