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I think only IF the simulation models are from the same technology AND from the same foundry (e.g. TSMC) AND of the same version released (e.g. v1.0.7) then you can be sure the elements are the same.
As suggested above, you might be better to start off from scratch to match the same...
@sutapanaki,
Thank you so much for the answer!
Can you help me understand why impedance looking down from n4 is inversely proportional to the loop gain of the bottom loop? Is it from the characteristic of series-shunt feedback config and its effect to Rin/Rout?
hmmm... I think sharing the simulation models might be problematic for me....
I was hoping that we can approach it in a more generic sense, kinda like analysing the effect of a miller compensation cap in a 2-stage op-amp, the effect on the poles/zeros can be analysed independent of the...
@FvM,
Attached is the simulation results for loop gain analysis at VLG.
As you can see there is a zero at around 1-2MHz followed by 2 additional poles afterwards. I'm wondering where this zero is coming from and also the additional 3rd pole.
@FvM,
Can you elaborate more on this please? I don't understand what you mean here.
If I don't have the circuit at the bottom, my VLG Middlebrooks analysis will not show a zero but with the additional loop at the bottom it will, I don't understand why.
@FvM,
Thank you for the reply. Indeed I am doing exactly what you specified with my simulations, using VLG and middlebrooks method on both loop, measuring ratio on both sides of VLG. The thing is, I see a zero appears on my simulation and I'm trying to figure out where it comes from, so in...
The op-amp is a simple 5 transistor op-amp, with gain of around 40-50dB, the total resistor is around 500K Ohm.
My schematic looks almost exactly like the sketch I provided except with values of the resistor & W/L size of the two MOS. What other information do you require? I'll do my best to...
Hey guys,
Please see the sketch of my circuit here.
I want to do loop-gain analysis (a.k.a. loop stability analysis) for the top loop. In simulation I simply put a voltage source (i.e. VLG) in part of the feedback and run the LG analysis (ie. AC loop gain).
My question is how to get my...
Hi All,
I'm wondering about which Monte Carlo setup will accurately represents statistical distribution in silicon on mass production.
There are 2 cases that I'm considering:
Case-1: Global Corner + Local MC
In this case I vary the Corner manually (ie. Typ, Fast, Slow, FS, SF) and run Local MC...
@wwfeldman, Thanks for the reply, sorry I don't have reference explanation for you, I'm looking for information myself.
- - - Updated - - -
Thanks for the reply.
Indeed I am referring to IC design, analog ICD specifically. To check transistor strong inversion, do you think I should check the...
Here is the sketch: link
I only drew 3 devices but conceptually they are the same. Basically NMOS connected in series.
The top most transistor will be in saturation and the other 4 will be in triode.
Let's say I have 5 NMOS with size W/L connected in series (stacked) with gate connected together, from what I understand this is functionally equivalent to a single NMOS with size W/5L.
In terms of saturation check only the top NMOS will be in saturation while the other 4 will be in triode. My...
Thank you for the explanation!
I don't actually intentionally go to subthreshold but the current requirement kinda force me into this region.
For a standard supply voltage variation (+/- 10%) and temperature variation (-40 to 125degC), what kind of spread on the current would you say you would...
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