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Recent content by kolouch

  1. K

    [SOLVED] SystemVerilog structure as a net

    Thanks, Dave, indeed, the example in section 6.7.1 confirms that a structure can be declared as a net in SystemVerilog. However, this example seems to me as rather hidden, I think more suitable place for it would be in the section dealing with structures, e.g. 7.2, where I originally tried to...
  2. K

    [SOLVED] SystemVerilog structure as a net

    Hi all, does anybody know whether it is possible to declare a structure in SystemVerilog as a net? It is written in the book SystemVerilog for Design, 2-nd edition, by Sutherland, Davidmann and Flake, p. 97, but I did not find any notice of it in the Language Reference Manual. Maybe, it could be...
  3. K

    Xilinx ISE with SystemVerilog

    Quartus II (Altera) is supporting SystemVerilog (in a limited but quite useful extent).
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