Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In dual-rail design, in a 2-inputs logic gates like an AND, the input signals have to be separated by a spacer '00' before calculating a new result with 2 others valid data (see figure 1, 2 and 3 here:https://pdfs.semanticscholar.org/f59e/f2b6f608c6928c45273a4439fb7cef1db384.pdf ).
Let's assume...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
