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BigBoss,
I havent tried modeling the transmission line using a resistor and inductor in series and a capacitor and another resistor in parallel. I think i will do that today. But as far as running transient simulations are concerned, i have done that and posted the image in my reply above and...
Dick,
One more thing. There are three models. Lossless, narrowband and wideband. I have not a lot of information about them. But from what i have studied, wideband seems to be the thing to go with. Plus i am writing the maximum frequency which the mtransmission line asks from me as 2Ghz(fmax)...
Hello everyone!
I am trying to model a differential transmission model for my lvds application. I first found out that for visual applications ribbon cable is the one commonly used for small distances upto 0.5m. I looked up the spec, dimensions and dielectric properties of the ribbon cable and...
Hello everyone!
I am working on the design of an IO with a differential driver and reciever with lvds approach. My requirements are to design the IO for optical interfaces.
Cat6a wire seems suitable for such an application as a transmission line. Therefore before starting the circuit design i...
Hello Everyone,
I am using Electric VLSI design tool to simulate and design some student projects. My question is about the schematic driven layout. Does Electric gives us this luxury or not?
Hello Everyone,
I am working on a Phase locked loop. for that i have to construct a VCO, which is a current starved one, and hence i have to calculate the value of currents at different voltages. I am having trouble finding various parameters in technology parameter files given on the internet...
i am encountering a strange problem while simulating my transmition gate which i will be using for flip flop, which will eventually be used for designing PFD of PLL.
the output gives some periodic distortion which even appears if there is no input !!
the schematic, symbol and output pics are...
i am burning this program in the controller 89c51 and o am setting all the pins of port 0 equals to 1 and the high voltage at port 0 is not ore than 0.7V while it gives 0V at low my code is
#include<reg52.h>
#define port P1
#define key P0
void main()
{
key=0xFF;
}
please if any one can help...
Friends,
i am having problems when i interface my comparator LM324 which is taking inputs from infrared sensors and giving output to the microcontroller. what happens is that without microcontroller the comparator gives good output like 3.6V and 0 V for a high and a low respectively...
@jmilito the case is (VDD-0)/2: and i want this voltage Vdd/2 to appear as the dc output of my amplifier not my input !!! i want to do this to obtain maximum voltage swing !!!!! it is a differential pair with nmos amplifying pair and pmos active load pair !!!!! i am working on 240 nm technology...
i am simulating a differential pair in CADENCE and having problems regarding the mid rail biasing and clipping . my amplifying pair is constantly biased at a voltage much higher than the mid range. Any suggestion regarding how can i ensure mid range biasing of my mos amplifying pair without...
i am needed to design a differential amplifier with active load a simple differential pair with a single ended output and then want to turn this amplifier to a unity gain buffer !!!!! after doing that i am needed to address to the stability operations !!!!!
PROBLEMS FACED ARE:
how to convert...
i am having problems in finding out the early voltage through graph !!!! i dont know what function to give in the calculator in cadence to find the exact value of early voltage !!!!!! Please if any one can give me an intuitive explanation of how to extrapolate the Id vs Vds graph to find the...
**broken link removed**
actually i am trying to build an invertor shown in the fig and i want to have power upto 100 watt so what do you suggest as for a heat sink
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