Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by kishoresai1996

  1. K

    Multiple sources for a clock

    Can a clock have multiple sources . It may be a generated clock or a master clock?
  2. K

    Design Compiler Command Needed

    or you can try get_attr [get_pins <clock_pin>] clocks
  3. K

    Timing Checks in primetime

    Think that i have a post routed database , and all the physical implementation is done, Now what is the most preferrable order to fix these violations?
  4. K

    Timing Checks in primetime

    What is order of fixing these violations setup, hold, max.tran and max-cap? and why?
See more

Part and Inventory Search

Back
Top