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Recent content by kishanb

  1. K

    What is the significance of double dummy poly on both sides for every transistor?

    Re: Double dummy poly in deep submicron technologies Hi velkumargn Could you just brief about what you said ? Regards Kishan.B
  2. K

    [SOLVED] Poly resistor instance is not recognizing in lvs working in PYXIS tool

    Poly resistor instance is not recognizing in lvs working in PYXIS tool it has PP RPO RPDMY RHDMY layers did anyone face this issue and for verification we are using calibre THANKS AND REGARDS KISHAN
  3. K

    [SOLVED] DTP violations in 20 nm technology

    DPT violations in 20 nm technology Hi all Can anybody explain what is DPT violations ? Should that be checked only when metals are very close to each other Thanks and regards
  4. K

    concept regarding Buried layer

    hi all How buried layer reduce latch up effect in nmos explain in brief ? dont say tht resistance decrease and latch up will reduce :-) Thanks and regareds Kishan.B
  5. K

    why there should be n well spacing

    wells at different potential needs to be apart orelse it will be in same potential shorting wells
  6. K

    concept regarding piezoresistivity

    Hi all I have a doubt as the piezoresistivity does not change in (111) plane and is minimum in all directions why do we still use (100) wafer what are the advantages using (100) orientation and how do i reduce piezoresistivity in (100) ? Thanks and Regards Kishan.B
  7. K

    [SOLVED] carry select adder applications

    carry select adder applications?:lol:
  8. K

    [SOLVED] How latch up can be avoided by increasing the rise and fall delay transitions?

    Thank you guys :)
  9. K

    [SOLVED] How latch up can be avoided by increasing the rise and fall delay transitions?

    Hi all Can anybody tell me how latch up can be avoided by increase the rise and fall delay transistions ? why does the threshold voltage increase when i place my transistor close to the well ? Thanks and regards Kishan.b
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