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nmos inverter
For inverter circuit with depletion type nMOS load, the gate and the source nodes of the load transistor are connected, hence Vgs(load) = 0 always? why is 0 ? anyone can explain it?
I need to design a circuit based on standard cell
- Use Silterra 0.18 um CMOS process technology
- Use tools from Mentor Graphics
- Circuit that need to be designed is count the number of times of bit changing from 0 to 1
- The input to the circuit is 4 binary bits
let the 4bit binary as A B C...
AM demodulator
I'm asked to design an AM Demolutaor which is used as product detector. Is that any link that provide this info?
below is the design, any idea to improve or modify to make it more better? thanks!
**broken link removed**
biot savart law finite wire
An infinite current filament carries a current of 3A and lies along the x-axis. Using Biot-Savart Law, find the magnectic field intensity in cartesian coordinates at a point P(-1,3,2).
dH = I vec{dl} x hat{R} / 4piR^2
let substitude hat{R} with vec{R} / R
then dH...
One question here,
is that any difference for the initial state for both Mealy and Moore machine if want to detect bit sequence 0110 ? Can direct set 0 to initial state?
sequence detector state transition diagram
Hi, I need to design a 0110/1001 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 0110 or 1001. The output 1 is to occur at the time of the forth input of the recognized...
Re: 2 stages op amp design
1 question come to my mind. what is the relationship between dominant pole and GBW? And also, 2 stage op-amp same as miller cmos OTA?
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