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Hey Dana,
1- pulse width =2u
2- The output kick signal ( VL=0, VH=0.8) is applied to the gate of a MOS ( CL=10fF)
3- The pulse width accuracy is not that critical ( 2u +/- 20%).
4- Power supply to the circuit is 0.8. Its can be increased t0 1.8 if necessary
6- There is no enable signal, the...
Hi,
I'm looking for a MOS transistor circuit that generates a kick signal at power on (when the power supply is applied to the circuit). Could you please point me to a reference/document that describes the behavior of such a circuit?
Hello All,
I am a newbie in AMS flow and Custom Compiler, and I want to simulate a system Verilog block in the custom compiler. In other words, I want to run the AMS flow using VCS. Does anyone know how I should start the work, which files I should prepare, and so on. Is there any tutorial or...
Hello everyone,
I was wondering what is the type of material and its dielectric constant that fills the gaps around the metal 6 layer in CMOS180nm TSMC.
Thanks
This is how I did it:
The layout that you see in the attached image is extracted. Then from the Virtuoso window, using a "CMC Skill" tab, I go for the "Layout/extract" tab and "generate a pin only schematic". This pin-only schematic is opened in a Virtuoso schematic editing window. From this...
Dear dick-freebird
The layout shown in the figure is extracted and, its symbol is generated using Cadence. The symbol is attached to the OTA.
Am I missing something here?
Thanks
1641336707
Dear BigBoss,
Thanks, But we know that there is a parasitic capacitance there, as there is in...
Hi,
Attached is an interdigitated electrode, implemented using metal 6 layer in 180nm tech, with a capacitance value of 6fF. It should generate a 70% change in the gain of an OTA, but when I connect it to the OTA, nothing happens. It seems that the Cadence does not recognize it as a...
Hi every one,
I am running Monte Carlo simulation on an OTA, and I need to have the numerical settings which indicate the magnitude of variations, or at least I need to obtain the range of parameter (process, mismatch, and temperature), which leads to the output histogram. Could anyone help...
Hi,
I am trying to layout interdigitated electrodes (attached image) in the top metal layer in CMOS 180nm. I was wondering how I can extract the parasitic capacitance between the two electrodes.
Thanks
Hi all
I need to find a commercially available Integrated OTA, which is able to load at least 10pF load capacitor. I wanted to see how can I find such an OTA n the market, and which parameters, I should be looking at?
Thanks
Hi everyone;
I am trying to place a padring around the layout of my circuit. Since all of the VDDrings and VSSrings of the pads should be connected together, I was wondering should I connect them manually, (Using which metal layer)? Moreover, what is PFILL and how should it be used?
Thanks in...
Hi every one,
I simulate a circuit in cadence and I run a transient analysis. I choose the stop time as 40ms, and it runs until t=40 ms, but when I want to watch the waveforms, they are displayed until 19 ms. Does anyone have an idea why is it so and how I should fix it? The circuit is an 8-bit...
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