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always @(posedge clk_wr or negedge rst_n)
if (~rst_n)
wr_almost_full <= 1'b0;
else if (reset_fifo_wr)
wr_almost_full <= 1'b0;
else if (wr)
begin
// set full bit a bit early to allow for the fact that the master
// will sample it whilst data is still...
where can i find a powerpc design forum?
my work is the designing of ppc motherboard .the cpu would be the freescale mpc,but i don't find good document of ppc motherboard.i need help.
thx.
i haven't jtag simulator and udm simulator , can i develop the mpc860 mini system?
if can use the jtag or system debug port(dck,dso,dsi)to develop the system?
where can find some document and source code?
thank you!
i haven't jtag simulator and udm simulator , can i develop the mpc860 mini system?
if can use the jtag or system debug port(dck,dso,dsi)to develop the system?
where can find some document and source code?
thank you!
i want to test some flash chip, these flash cann't work right, i program the flash and read the flash, but the whole flash is A7E7, it isn't my program file's content.
how should i do to determine if the flash is good or not?
thanks.
i want to design a LQFP80 thremal enhance pack, it has a 1x1(cm2) pad under the package for thremal enhance. how to design the package, and the what's the relation between the symbol's pin and package's pin?
and how to place a shape without mask solder?
thank you.
i don't think it's the best way, because i need a lot of work (such as filter)to do after mixer.
now i'm study the if sample tech, this seem to be a good way.
how do you think of it ?
thank you.
the 2fsk signal is :s(t)=sin((2*pi*60000000+a(t)*700000)*t),and 67m is '1',53m is '0'.
i need to design the demodulate circuit .
i look for the demodulate chip, but the the chip's f0 which finded in web is too low ,just khz. and the all digital pll need a very high frequency clk which maybe...
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