Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Unconnected Ports
After doing P&R with Astro and save its hierarchical netlist as verilog file, you can find some unconnected ports generated at the input and/or output ports. If it is at the input port, that should be connected to VDD or VSS (I think it is usually connected to VSS). But if it...
someone knows cts format for astro?
I can't understand what you wanna know.
In astro, there is a astro technology file like *.tf
Doing CTS in astro, I think you don't need any extra technology file.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
