# Recent content by KillaKem

1. ### 12 state counter design

Ended up doing the 0-11 counter.
2. ### 12 state counter design

I want to design a synchronous counter with 12 states and synchronous reset by connecting the overflow signal ( CT =15 ) directly to load input ( /M2M1 ) so that I can start the counter at a custom state, what I'm thinking of doing right now is just put flip-flops pre-loaded with my predefined...
3. ### Open Loop gain in Feedback control system

You make it sound like it's true for only H(s) = 1 when it works for all H(s). If G(s) = (s+2)(s+9) and H(s) = 1/(s+6), then OL poles = -9,-6 OL zeros = -2 Root locus of CL system will travel from [ -9 and -6 ] to [ -2 and $\pm$Infinity ], H(s) just changes the path the locus will take...
4. ### Open Loop gain in Feedback control system

Isn't that how closed loop poles travel, how does the root locus of G(s) = (s+2)(s+9) look like? Consider this, lets assume my plot is correct, if i wanted to find the value of K at the point s = -3 in the root locus plot, I would use the formula \[ k = \frac{\prod |s - p_i| }{ \prod | s -...
5. ### Open Loop gain in Feedback control system

I meant to write characteristic Equation ( GH(s) ) = 0 instead of just GH(s) = 0. Lets take a simple example of G = (s+2)/(s+9) , H = 1. Open Loop Pole = -9 Open loop Zero = -2 The root locus of the closed loop equation ( G/(1 + GH) ) will thus be a straight line travelling from -9 to...
6. ### Open Loop gain in Feedback control system

The way I understand it is that in order to solve 1 + KGH(s) = 0, you first solve GH(s) = 0 which will give you the open loop poles, those are the poles were the root locus plot will begin ( ie the poles for K=0 ) Or you can consider the fact that in root locus plots the value of K can be found...
7. ### Open Loop gain in Feedback control system

Consider a standard feedback control system with controller gain K(s) and plant transfer function G(s) with unity negative feedback( ie H(s) = 1 ). The characteristic equation of the system is 1 + KGH(s) = 1 + K(s)G(s). Now when finding the root locus you find the poles and zeros at K=0 ( Open...
8. ### creating two diffrents clocks

I don't really understand what you are trying to do, are you trying to derive one clock from another one? e.g you have a 20MHz clock and you are trying to derive a 5Hz clock from it so you can use the 20Mhz clock to power one component and the 5Hz clock to power another.If this is what you are...
9. ### How to use global parameters in System verilog

I have modules that define a parameter N, I also have an encapsulating module that instantiates all the other modules and it also defines the parameter N, so the problem I'm having is that every time I want to change the value of N I have to go into all the modules one by one and change N's...
10. ### SystemVerilog - Setting an output high in future clock cycle

How do I set an output high for the future clock cycle in system verilog.I would really want this module to only consist of one code block. Eg. I have one input signal A, and two output signals B and C, if A = 0, I want B to go High in the next clock cycle but if A = 1, I want B to go high in...
11. ### Common Emitter Amplifier Design

Yeah, I guess it was a loading problem, I increased the R1 and R2 resistors in the common collector amplifier to values over 100k and Re to 5k and the circuit simulated well.
12. ### Common Emitter Amplifier Design

The output drops at the output of the amp when I connect the buffer to the end of the amplifier in simulation, I have not connected a load to the end of the buffer yet. Ce = 10microF Test_Freq = 1Khz The output drops at the output of the first stage. Vin(AC) = 0.1v peak to peak Vout(Stage...
13. ### Common Emitter Amplifier Design

But I need to pick the Re2 value carefully because it will help me better choose the capacitor Ce properly, I want to make sure I have all my components designed properly.Right now the values I've given together with a Re2 value of 3.9K give me a small signal gain of 6.7 when I simulate them on...
14. ### How Can I Design Common-Emitter Amplifier ?

Isn't the DC gain the one that is - (R1/R2)? The gain Av refers to the AC gain that you get that from small signal analysis, Av = - gm * ( R1 || RL ). Where gm = 40Ic
15. ### Common Emitter Amplifier Design

I know, AC gain = Rc/Re1 = 6 Re1 and Re2 will determine the bias point but I first need to pick a suitable value for Re2, and for that I will need to use KVL going around the output loop, and for that I need to get VCE.