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I have to design a PCB that should house a chip to be tested through FPGA (to be placed on the board itself as well).
I have written down a bunch of test steps to be performed but I have no idea how to start the PCB design. Is there any material on this topic (not PCB design in general but for...
I have a mixed signal ASIC with one full custom section designed in Cadence Virtuoso and another one designed in Verilog to be implemented with the standard cell library of my technology.
Now I must put the two things together for backend.
I have already generated the lef file for the full...
I am using Cadence Abstract Generator to generate the LEF file of a macrocell (full custom) which I want to put along with another one (standard cell) inside my chip.
My full custom macrocell is made up of hundreds of cells (basic gates and FFs) and has a size of around 900 x 330 um2.
When I run...
Hi everyone,
I am trying to generate an abstract view for a macrocell with Abstract generator. After loading the library I get the following errors:
*****************************
ERROR (ABS-216): There are insufficient metal layers defined in the current design. You must define at least...
Hi everyone,
I have a verilog code which I simulated with Icarus tool so all I have is a logic level simulation. This code is related to a digital part of an ASIC which I'm implementing in Cadence Virtuoso.
My questions are:
1) How can I bind my verilog code to the standard cell library of the...
Re: .wav file in Cadence
Hi rca,
thank you for your reply.
Could you suggest any documentation which provides information on how let verilogA communicate with my .wav file? I have no expericence in this sense. In the Cadene help I haven't found any document when using "wav" as a keyword.
Thanks
Hi everyone,
I need to know if it is possible to use a .wav file as an input to a circuit in Cadence Virtuoso 6.1.
This file will be used to simulate a signal coming out of a silicon photomultiplier with its proper statistic. I need it in order to check if my circuitry (a time to digital...
Does anyone have experience in generating the unified techfile (qrcTechFile) for QRC usage (parasitic extraction)? I have installed EXT and I can see the QRC command in my Assura menu but my extraction run fails. I think I have generated the techfile in the wrong way...:sad:
My tools are...
I've got a similar problem but I'm not sure how to fix it.
I'm using Cadence 6.1 and working with Assura 4.1. I've just got EXT 9.1 installed as well but after launching RCX the run fails with the following warnings:
*WARNING* No library model for device "N_PG52P5_LLHVT".
*WARNING* No library...
Hi hall,
I installed the EXT software for parasitic extraction with Cadence 6.1. After opening my layout view, in the LOG window I can see the following warnings:
*WARNING* (LCE-2011): Cannot determine the function of layer 'AL_RDL' in constraint group 'virtuosoDefaultExtractorSetup' of...
In the parasitic extraction window it is possible to choose among different output views. I've read that usually one selects the extracted view option but I can see that 2 similar choices are available: Lvs Exctracted View and Exctracted View (cfr. the attachement). If I select the first one...
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