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Hello,
I have designed my network on chip in verilog language using xilinx Ise. now I want to evaluate my design with parsec workload?
could you explain to me how can I impose the workload to my network step by step?
thanks in advance...
hello
I have implemented a network on chip in Xilinx Ise (the routers and the links). the codes are in verilog language.
now, I want to measure full-system performance, and leverage FeS2 (simics)
for x86 simulation (I have simulated NoC in xilinx ISE before), and then run PARSEC workloads with...
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