Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
We have FPGA prototype. But due to the limited budget and team experience, we don't have a proper emulator to run the full design. We can only fit 1/4 of the core design (excluding the peripherals) in the largest available Altera S10 FPGA. That is the reason why we are worrying the quality of...
Thanks for the advices from both of you. Yes, we have unit test for all the individual modules where the parameter ranges, margins, typical value, etc. are tests to cover the combinations. It is nice to know that others have worked out how to address these large parameter space issues. Thanks!
Hi all,
My pervious knowledge is to break the system in to small pieces (may be hierarchically) to a stage that the feature points cannot be further decomposed. Then create a collection of test cases to cover all these feature points.
Now we have a system with about 10 modules (each is a DSP...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
