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Thanks ducvilla and erikl. Really appreciate your time. How can I control the drop Vsd of P1 in the figure (i.e. manipulating W/L or Vgs) or across a transistor in general?
I am a newbie in both analog design and cadence. I'm having problem while simulating this simple single stage CS amplifier as shown in the diagram. Here, P1 is in saturation but N2 isn't. How can I drive N2 into saturation also. Please suggest me, what parameters should I play with.
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