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Recent content by khaila

  1. K

    how to use FPGA to evaluate power or performance of an ASIC?

    FPGA is based on LUT and FF while ASIC based on gates only. FPGA used fixed MEMORY blocks while ASIC is custom. FPGA PLLs differs than ASIC PLL FPGA production technology is completly deiffernt than ASIC. So it is not possible to evaluate power of ASIC based on FPGA.
  2. K

    How do you implement X^2.5???

    you suggerst two soluations: 1. implement all the equation by using memory only. 2. using less memory but using also 3 multipliers. which soluation is better for ASIC and whichfor FGPA? is there any other consideration?
  3. K

    How do you implement X^2.5???

    I have asked about implemetation of X^2.5 while X is a vector of 8-bit. No alhorith implemetaion is required. I have suggested the following solution: X^2.5= X^2*X^0.5 for X^2 I will use simple multiplier(X*X). X^0.5 I will use ROM. then I will multiply the results.
  4. K

    I want to buy FPGA in Egypt

    Yes it is for Xilinx FPGA. the model is DLC9G.
  5. K

    I want to buy FPGA in Egypt

    i want to buy fpga in egypt I can send you my cable that I am not using. wanna it???
  6. K

    merge some data with the bit file

    Why do you need such this data??? what the content of this data??? You should take care about programming the FPGA with incorrect data. You may cause unexpexted result in FPGA. Generally when programming the FPGA, the programmer should take to erase the content of the FPGA to insure that the...
  7. K

    calculation of net delay..........

    Gate delay(LUT) can be calculated from the vendor datasheet. The net delay is never calculated in advanced because it depends on the place and route so it is keep unknown till you have the result of the PAR; then you will have a detailed report regarding each net/trace.
  8. K

    How to implement SW_reset in Verilog?

    Re: SW_reset This is the way that I am using SW_RST. In addtion: 1. I sample the OR output gate to same clock domain. 2. as a global reset is synchronized; it will be traeted in the process as asynchrnous one to insure that evently reset can NOT affect FF at S/H time window. 3. limiting the...
  9. K

    Is it correct to instantiate a module within 'always' or 'if' in Verilog?

    Re: doubt in verilog sure NOT. It impossible.
  10. K

    JTAG connection ereror in FPGA

    sorry but the most common problem is people are confused how to connect TDI and TDO so you may check if they are connected propably. :D
  11. K

    Unknown identifier "log2"

    pad_power2(4) You just have to include proc_common_pkg: If proc_common_pkg.vhd is complied to WORK directory so: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.proc_common_pkg.all;
  12. K

    Looking for documents about ECC memory

    May anyone recommend me on a free core of ECC??? Or at least if you have good DOCs about it.
  13. K

    Using System ID core for Altera Startix-II without NIOS

    Re: System ID Core. used for version control. when any external peripheral is using this FPGA should now if the current image is modified or not.
  14. K

    Using System ID core for Altera Startix-II without NIOS

    I am using Altera'Startix-II with out NIOS. I only using its memory and logic. I want to build a component that holds the version of the current FPGA image. this version is incremented every new version of FPGA so I can read it by Read Only register. I have no flash. In the past, when I used...
  15. K

    How to display fraction in VHDL simulation???

    represent fractions in vhdl how supposed an unsigned vector A_UNS which represent 4.3 in form q.r: 4 : represents 4-bit of the QUOTIENT 3 : represents 3-bit of the REMAINDER for example: decimal vector 9.125 is represented in binary as A_UNS="1001.001" the simulator will show A_UNS as 73...

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