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cpha is listed in the genrics and is assigned to 0 and i can show you my simuluation waveforms with cpha and cpol
1681992551
sorry i will fix it for future posts seems like i cant really edit it now
Hello all I am a new firmware engineer trying to get an spi transaction to occur for this module that i found by Digi key however my bit counter signal although its supposed to start at 1 or (0000000000000001) it starts at 2 (0000000000000010) I've been trying to figure out why it starts at 2...
Hello I am trying to create a testbench for this VHDL code of an SPI slave that I found online for verification and so that i can implement it into a project that I'm working on. I've gotten my testbench to compile and run and to drive signals but the data transfer and all the MOSI and MISO...
why isnt the value zero included as an integer as well? there are 24 values in the range of zero to 23 right?
1680696300
Also might you know the reason that my MOSI, MISO and SS lines dont appear in sim is there a manual way to put them in maybe?
Hello, i am trying to learn how to implement an SPI Slave for work. this is the my first time writing any module so i decided to try to build a test bench around someones slave module i found online. i wrote the test bench but when i go to simulation i get a bunch of signals showing U and im not...
Ive attched a picture of the error message i get during compilation and also what my waveforms come out to look like. ive tried looking for a way to manually insert the MOSI, MISO wave forms but i couldn't find anything
SPI Master Module
library ieee;
use ieee.std_logic_1164.all;
entity fsm_spi is
port( clk, rst, rd_enable, miso: in std_logic;
mosi, ss, sclk: out std_logic );
end entity;
architecture logic_flow of fsm_spi is
type state is (st_idle, st0_txRead, st1_txAddress,
st2_rxData);
signal...
SPI MASTER Code
library ieee;
use ieee.std_logic_1164.all;
entity fsm_spi is
port( clk, rst, rd_enable, miso: in std_logic;
mosi, ss, sclk: out std_logic );
end entity;
architecture logic_flow of fsm_spi is
type state is (st_idle, st0_txRead, st1_txAddress,
st2_rxData);
signal...
Hi all im trying to write a test bench for a SPI Slave module i made but i keep getting a bug saying expecting function or procedure or impure or pure at line 11
below is a copy of my TB
library IEEE;
use IEEE.std_logic_1164.all;
entity Spi_practice2_tb is
end Spi_practice2_tb;
architecture...
Hi im pretty knew to VHDL and im trying to simulate the code that i wrote for an SPI master but when i go to wave simulations in model sim the most important waveforms dont show up MOSI, MISO, and SS. the only reason that i see that they might not be appearing is because i receive a fatal error...
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