Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by kgeorge123

  1. K

    Front End ASIC Design or Back End Design JOB,

    Hi All, I was trying to do pros and cons of Front end ASIC design vs Back end. Can you please help me in deciding which job should I choose? Can you tell me which one has more scope in the long run? Which one is less likely to get outsourced to countries like India and China? How about...
  2. K

    Hold time problem with Verilog netlist

    Re: hold time problem Yes you do not have to worry about Hold time or high impedances or any Xs in the simulation before the start of reset. The simulation is dependent on the design libraries we are using. However in real chip nothing matters before reset. Thats what we did in our simulations...
  3. K

    Pmos is twice of NMOS

    I think Giri has explained it quite rightly. The width of PMOS is almost 3 times that of NMOS to get comparative rise and fall times and switching of operation. To give you an example.Traditionally nandgates are used as the basic desing gates(Universal Gate) compared to norgates(also universal...
  4. K

    IR-reducing problem in Magma software

    Re: IR-drop problem IR drop values are quite related to the process technology. For 3.3V 0.25 um process 100 mv is not a problem. However we definately need lower values for 0.13um process somewhere around 60mv(this last no is my guess).
  5. K

    what happens if hold time greater than setup time

    Dude, Setup and Hold times have not relations with each other.It is the property of the FFs in the libs. Check below
  6. K

    Optocoupler or Optoisolator for Audio

    optocoupler audio Thanks E-design. I have already looked into that(Optoisolator made up of ADC and DAC). The problem with using such a device is that there are THD and noise introduced by the DAC and ADC and this will adversly affect your audio(especially when they havent mentioned the...
  7. K

    decopuling capacitor in power circuit

    Say I have one regulator from where I am supplying the power. And I have three gounds Digital(<50MHz) ground Analog(<20Khz) ground and RF(<1GHz) ground. And say that I want to design a low pass filter which filters out all the frequencies if possible above 0Hz.What caps should be best? Now my...
  8. K

    Verilog clarification request

    constant-time up/down counters verilog 1. If you have different times scales for testbench and module usually testbench will take the priority and your simulator will give a warning if you have set it up that way. But from implementation point of view it is a good idea to have all the same time...
  9. K

    Optocoupler or Optoisolator for Audio

    analog opto isolator Well Kender. It is for high voltage application. In audio what we most care about is linearity, SNR figure of the Optocoupler, THD and how to eliminate ageing.
  10. K

    Optocoupler or Optoisolator for Audio

    audio opto-isolator Thanks I actually read that. But didnt find a good one yet with a good linearity. Ageing still seems to be an issue.I was wondering if there is any other techniue to acheive audio isolation. Transformer isolation doesnt seem attractive because it takes too much space and may...
  11. K

    Optocoupler or Optoisolator for Audio

    Hi, We have two channel audio to be seperated from the final stage audio amplifier. Now becase of different products the final power ampifier keeps on changing and we come across gounding loop/ humming noise. I know that optocoupler could be used to eliminate this. Does any one knows any good...
  12. K

    Optocoupler or Optoisolator for Audio

    audio opto isolator Hi, We have two channel audio to be seperated from the final stage audio amplifier. Now becase of different products the final power ampifier keeps on changing and we come across gounding loop/ humming noise. I know that optocoupler could be used to eliminate this. Does any...
  13. K

    How to deal with IO and Core with diff supply voltage?

    Yes you will have to tie the power cells /PADs to VDDH and VSSH which is you are saying for IO power. Basically you will have seperate ports on your topmost level entity where you will be getting this IO Power. Then later in RTL you will have to tie the IO cells to this port/net..
  14. K

    Help on Low power memory design

    Low power memory design is a very advanced concept.It varies depedning on what type of memory you want to design.Is it SRAm or EPROM or DRAM?? Low power involves proper frequency of operation.Efficient recharge cycle and Controlling various variations (Charge and discharge)happening across the...
  15. K

    Power Estimation after P&R

    Thank you for the tools info.At what stage can this power can be calculated.Is this like just at the GDSII stage or before it. I wish to know if it would model the current capabilites of the pads and output drivers etc. Added after 1 hours 50 minutes: Are these tools able to model High...

Part and Inventory Search

Top