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The first one might make sense. but I think not for the reason you state, I think it might be a protection against a board being off by 90 degrees.
Here's what our assembler asks for. They do ask for fiducials to be tinned which agrees with your second question.
Fiducials
Fiducials shall meet...
In your working project in '09, you can create libraries of the parts used: For the schematic: Design -> Make Schematic Library, and for the PCB: Design -> Make PCB Library. ( or Design -> Make Integrated Library for a combined compiled library ) They will become part of the project and...
I recently did some designs with thermal vias under the thermal pads; the thermal vias went to copper on the bottom side and in some cases also to the ground plane layer, with no thermal relief. I was worried that the assembly house might have trouble with the soldering, but the boards came...
Solder mask is a "negative" layer, so any objects placed there will cause an opening in the soldermask. I don't know of any way to do what you want with rules. With parts that need heatsinking, I put a base-level heatsink in the footprint, and I manually add to it as space allows.
FYI I...
1. Altium by default tries to enforce the convention that crossing wires are not connected, only "T" junctions, and that you have to manually place a junction if you want to force a connection of 2 crossing wires. If you want crossing wires to create a junction, you can go into schematic...
If the via is part of the footprint, try clicking to select the component, then right-click -> Properties and uncheck the box "Lock Primitives". See if that helps.
Re: Duplicate PCB design
Yes, "Copy Room Format" copies everything. Before you copy, you have to manually make the second room the same size as the first.
---------- Post added at 09:50 ---------- Previous post was at 09:32 ----------
You should also be aware how signals are handled which go...
Re: Duplicate PCB design
If it's 2 different channels on the same PCB, what you want to do is make the channel design a single lower-level sheet (it can have subsheets). Then on the top level of your schematic, place the lower-level sheet with a REPEAT(LOWER_SHEET_NAME,1,2) designator. This...
I agree with btbass, I would also add that you need to identify and carefully handle the specific traces that are likely to cause the most trouble, i.e. the lowest-level signals, before they are amplified. These have to be routed very carefully, and kept away from not only each other but...
The only thing I can suggest is to generate a netlist from the schematic (Design -> Netlist for Project -> Wirelist, then look under "Netlist Files" under "Generated"). Inspect it manually to see if it matches what you think the schematic says. If it doesn't, the problem is on the schematic...
In 3D mode you can File -> Save As -> Export STEP, and it will save the entire PCB as a Step model which you can read into another program (i.e. Inventor, and I think SolidWorks or Acrobat Extended). It doesn't look quite as good as it does in Altium, all the parts are there but you can't see...
Altium's PCB Design Rule check will ensure that the PCB matches the schematic's netlist. but to do that:
1) You have to make sure the schematic is correct. the warnings are helpful, but it can't read your mind, and anyway they only flag errors if the pins have their functions defined in the...
Those vias are primarily thermal; you can get the current in with top layer copper but you might not be able to get the heat away. I wrote up a note on how to do thermal vias in footprints in Altium, but even if you use another EDA package you might want to check out the links mentioned...
If you can keep everything on the top side (traces and vias), and you just want a bare PCB under the plate, you can place a keepout on the bottom... Place -> Fill -> Tab -> select Bottom Layer and check the "Keepout" box. I think you can even put this in the footprint. That's the best...
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