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If you synthesis with a standcell library, you can find the report about the area, then you find the area of NANDX1(drive strength is 1, NAND gate), the last thing you have to do is use the full chip area dived NANDX1 area, you can get the gatecount of you design.
vcs timescale overwrite
I think you can use the same timescale in the full design, just modify the most little scale as the timescale for the full design.
I think the effect on other file with large timescale is only slow the simulation, it wont affect the simulation result!
wgl format
In the design, there are some logic to test PHY, so I use simulation to generate VCD file to generate stimulus and get results for tester. But test house want to get WGL format.
I have Encounter Test tool to generate FULLSCAN test pattern file (WGL format), how to translate VCD...
digital power on reset logic
It sounds good, but will it work in practice ?
I think maybe we can also use this to generate a enable clock to gate the full chip clock to help the full system not work before reset.
for RTL compiler:
in you srcipt;
include load_etc.tcl;## this script is from cadence Application Engineers, in /your_rc/etc/synth/ae_utils/load_etc.tcl
insert_io_buffers -remove_assigns
Re: c@dence
You can edit a filelist file.
for example:
### filelist
./top.v
./**.v
./**.v
### endof filelist
then you can use
ncverilog -f filelist
that 's ok!!
I have just involved in a project , that when standby cutting the power supply for the most modules and only resever power for system control partion. This will decrease the leakage power. But we have to insert isolation cell to hold some control signals (output from the cutting power supply...
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