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Recent content by ken811125

  1. K

    gate level simulation error

    when i do post-route simulation,i got a timing error... Warning! Timing violation $setuphold<hold>( posedge CK &&& (flag == 1):4132 NS, posedge D:4132 NS, 1.000 : 1 NS, 0.500 : 500 PS ); File: /usr/cad/ENV/CBDK_TSMC018_Arm_v4.0/CIC/Verilog/tsmc18.v, line = 6398...
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