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hi all
on 28th mantalova systems is conducting interviews for vlsi design engineers. it consists of test followed by interview.
if anybody hav the previous question papers, plz do help me......
thanks in advance...
Re: help in a VHDL code
use two more signals like a,b. and use xor2 userdefined component
uuuuuu : xor2 port map (a,b,x3);
process (data_in)
begin
if x2="111111" then --o/p of counter
x<='1';
else
y<='1 --take two variables x,y';
end if;
end process;
a<=x;
b<=y;
i think this code...
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