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Re: circuit using standard digital lib for creating the dela
thank you for respond
I solved this problem already
in real, for 45 nm tech. process I was not need so big delay so I do not care about the number of used cells for it right now
thanks
Hello All
I need to use a delay component (few ns) using standard digital library cells (I know, that the delay value due to the process variation will be very different, but I can swallow it... )
is any other more effective circuit to create the delay instead even number of inverters...
SF/FS are not a montecarlo simulations but corners
on the one case the nmos are slow an pmos are fast (all transistors on the simulated scheme)
on the other case in revers the nmos transistors are fast and pmos are slow
on the case of monte carlo mismatch simulation the different parameters...
hspice monte carlo
Hello all
I have some question about hspice monte carlo tran simulation
I need to start the simulation from the specific run (like a specific seed ...)
f.e. in generall I need 100 runs of tran simulation (but that require too long time)
may I in some way to run f.e.
first 50...
Re: clock division
basically author asced about clock division
if you read my previous post, I do not recommend any way to use divided manually clock :)
but if you are realy need it then flip-flop based divider has to be simpler then other for a not high frequency schemes
Regards, Dan
Re: clock division
ASIC design
using only flip-flops for the CLK dividing. the skew is not worst after dividing
BUT, effect from jitter grow up and realy more important
that is why do not recomment to use any dividings or use dividing with a synchronization (with precursor CLK)
becasue of the...
transient cadence ade
I also do not understand clearly this one but spectre som adaptive choosing the time step (even if you set it handly)
and time step depend from the processes in circuite ..
probably you enable the "Transient Noise" advantages etc, your time step depend from that and that...
probe tran
.probe=0
saving all NETs values (voltage)
and you do not have to define exactly points which you want to view
this kinf of TRAN simulation is very slow but good enough for "debug"
if you using
.PROBe=1
then you also have to use
.PROBE TRAN
+V(what signal you need)
+I(what signal...
Re: difference on the post-layout and pre-post-layout simula
I have to point
that info was realy helpful and we found more bugs then expected :D. I'm newbie in that are so that is why so simple things were new for me.
anyway, it's working now and I thnx for all for your attention and help...
what do you mean noise ?
values '1' or '0' distributed randomly ?
is yes, then it's simple to youse a two ring oscillators where is slower sampling high freq ring osc with needed for you frequency
good luck
Dan
Re: difference on the post-layout and pre-post-layout simula
that is just cleaning an output
but for me the clear work of every cascade is important ..
in real I found the problem (in the middle components between the RO inverter - in my case that is not clear RO)
thanks for all for your help...
Re: difference on the post-layout and pre-post-layout simula
added.... values were related to the real caps values between the cascades...
the difference was not so much :(
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