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I'm working on a project that calls for an Intel Arria 10 GX part. All processing will be in an external ARM (This is a port of an older design, which had an external uC).
Unfortunately, I am having trouble getting the GX parts, but the equivalent SX parts are available (higher cost). Since I...
I successfully used the opencores I2C as an add-on for a customer. Worked, although I had to mod it a bit. I'd say that the lack of support is the real difference. If it's a complex thing you probbly won't find it in opencores anyway.
"Should we use UVM for even simple designs such as SPI or...
A much simpler example is the 6502, and there are some good guides to the architecture. A number of years ago I used this to build a 6502 into an ASIC, back before everything had ARMs. Worked great, if you don't mind 8-bit math.
**broken link removed**
I use CORDICs all the time. Good, fast, easy to implement using nothing but adder/subtractors. You can do several stages per clock with modern FPGAs. There are pipelined forms and recursive ones. Good for FFTs.
Depending on the form you choose, it can be used for vector rotation, vector...
I'd considered that, but the required switch response time is on the order of a microsecond, and 400KHz serial commands are too slow. My qualms with this is that I have no real experience with I2C and don't have a good feel for how actual parts behave. But thanks for your response.
According to the spec, if both clock and data are high, I2C is idle. Data going low while clock remain high is START. data going high while clock is high is STOP. Otherwise all data transitions are while clock is low (and read on posedge clock).
I want to cheat and use false start and stop...
I have a application where I have to talk to an I2C device at the end of a cable AND also toggle a switch. It seems difficult, physically, to get the desired third control wire into the cable. I have SCL, SDA, power and ground.
1) I deal with the switch only at times the I2C is inactive.
2)...
Re: ModelSim or qu(at)rtus II
As a an EDITOR, I'd use an editor like Slickedit.
For making an Altera FPGA using VHDL, you need to have Quartus. You probably will want Modelsim, although the version that comes with Quartus may suffice.
To answer my own question, the Virage memory library I was using has a discrepancy between the verilog view and the synopsis view, where the $removal lines are not present in the verilog, but REMOVAL statements are present in the lib. This causes errors when backannotating the netlist with the...
I'm trying to use ModelSim 6.1a to do gate level sim for an ASIC design. The RTL sims just fine, and the synthesis has no errors and all warnings are understood.
I'm using Synplify ASIC 5.26 for synthesis. My design is to be implemented using a set of Virage libraries. I'm having a problem...
My NAV 2007 license expired and I installed NAV2008 on my work computer. I specifically enabled the local net and my home IP for anything (NAV2008 actually defaults to enabling the local net now).
However, if I try to access the machine with Remote Desktop, or locally use some FlexLM managed...
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