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Recent content by kbx

  1. K

    A gate driver with limited swing

    Hi, I am working in a process with Vgs_max = 6V. However I have a supply of 7V. My input clock is 0-to-3V swing. What would be the best gate driver architecture to convert this input signal to drive a PMOS, such that its swing would be (approx) 1V-to-7V? Thanks, KBX

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