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Recent content by kaushiksangam

  1. K

    What is the simulator required for PERL?

    perl simulators You can run Perl from any UNIX machine. You also an find many simulators for perl on windows. You can find free windows version. Download that and try running sample perl scripts.
  2. K

    Fixed point operations in C

    It is about the implementation of a Brain State in a Box (BSB) algorithm. Before implementinng this in hardware, i would want to emulate the same in C. Already have implemented algorithm in C through floating point oprations. I can also send you the code of the implementation.
  3. K

    Fixed point operations in C

    I want to emulate an algorithm in C before actually writing to hardware. This algorithm invovles lot of multiplications and additions of real numbers. Hence, I want to use fixed point operations(to represent real numbers) in C to emulate the algorithm. Can someone please tell me or give me...
  4. K

    Conersion of Real number to integer number in VHDL

    convert real number to integer I have to implement a Brain State in a Box attractor algorithm in VirtexII pro. I would have to code this in VHDL. This algorithm involves lot of array multiplications of the numbers from the range[-1 1], but Virtex II pro has a 18*18 bit signed multiplier...
  5. K

    Conersion of Real number to integer number in VHDL

    vhdl real to integer I want to convert real numbers to integer numbers in VHDL. The real numbers that I am using are between -1 and +1. For example I would like to convert the number -0.67857 to a 18 bit signed representation. Can someone please help me otu with this.
  6. K

    How to use XILINX EDK with XPS and Xilinx ISE?

    Hi all, I would have to use XILINX EDK kit. have fully installed the XILINX Platform studio(XPS) and would like to use it with XILINX Virtex 4 board form AVNET. Please suggest me to get more information on how to use the board with the XPS and XILINX ISE installed. Also, would...
  7. K

    Help me convert this code from VHDL to Verilog

    Re: Doubt in verilog You could use if else if statements to do this in verilog. if(sci_read==1'b0) begin dbus = 8'bzzzzzzzz; end else if(addr==2'b0) begin dbus = rdr; end else if(addr==2'b0) begin dbus = scsr; end...
  8. K

    Fixed point to Integer conversion in VHDL?

    conversion real integer vhdl since, I would have to multiply real numbers from the range -1 to +1. I would have to represent these numbers to integer numbers (representation) and multiply them because, I would be using VirtexII pro for the implementaion, which has only 18bit*18bit integer...
  9. K

    Fixed point to Integer conversion in VHDL?

    vhdl sfixed conversions Hi all, I have to write a program that involves lot of multiplication with numbers from the range -1 to +1. I think, I would have to convert these fixed point numbers to integers and then multiply and then convert back the result to its deimal value. If I have...
  10. K

    Information about SystemC

    Re: SystemC You can get more information on this from , www.systemc.org. A good book for learning systemC is A SystemC Primer by J.Bhasker
  11. K

    VHDL function to convert an vector datatype to integer

    Is there a function to convert an vector datatype to integer and vice versa.
  12. K

    are there any visual C++ to VHDL converter out there?

    c to hdl converter I think this link might be useful to you. https://www.aldec.com/solutions/c-baseddesign/ Also, you ca download the trial version from that link and play around with the tool.
  13. K

    VCS error as simulation is not progressing

    Re: verilog You can specify your simulation time $finish, in your test bench. specify it as $finish 9000; Which would run for 9000 counts...
  14. K

    Genetic Algorithm on XILINX

    I want to implement a genetic algorithm on an FPGA. I have a very basic idea of the architecture of the hardware implementation. I would appreciate if someone has some idea or has a source code of the algorithm, which can help me progress on my research. Implementation can either Verilog or...

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