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Recent content by kartikkg

  1. K

    ARM 7 generic cpu ,keil Uv4

    yes i am using a very tiny portion and i am learning it , to begin with i am coding small things , plz help out Added after 3 minutes: plz give a proper answer
  2. K

    ARM 7 generic cpu ,keil Uv4

    i am practicing small arm 7 programs and have selected the first ARM 7 generic cpu as target device , i am having trouble with LDR and STR instructions as they are givein error 65, memory access violation , the trouble is same for cortex m0 or any other processor ,The program Is in "ASSembly...
  3. K

    keil arm7 help in acess memory

    i know difference between ram , rom etc what i want is a solution and not a weird lecture which addresses no issue , Can anybody who knows for real ,provide me with a solution? i ve enable rom ram settings in the target device and given them address range too, but yet this problem persists...
  4. K

    keil arm7 help in acess memory

    i am a novice at keil , i am learning arm 7 assembly level program , i want to know hot to read and write into memory ,either rom or ram AREA ARMex, CODE, READONLY ; Name this block of code ARMex ENTRY ; Mark first instruction to...
  5. K

    not gate - Inverter ?help

    keith which is that software u sued for schematics u are getting the right curve for it. But the output should be taken from the junctions of the two transistors in ur pdf its marked Q1-G , if u taking from there only its corect. Can u plz aplly clock and give me the output
  6. K

    not gate - Inverter ?help

    thanks keith they are the models present in the multisim and they are virtual . i think they got the ideal characteristics i am using multi sim 2001 i hope that the edition should nt be a problem **broken link removed**
  7. K

    not gate - Inverter ?help

    hi Keith i am not good at this S/W can u plz check the ckt yourself in multisim and do the dc sweep i did it but i dont know what to figure out with it ! I would be thankful to you :)
  8. K

    not gate - Inverter ?help

    is the schematic correct?? i am still not getting not function from this
  9. K

    not gate - Inverter ?help

    **broken link removed** this is the image
  10. K

    not gate - Inverter ?help

    hello i am using multisim software for simulating a NOt gate (inverter) , what i am doing is taking a virtual depleted mode nmos trans and shorting its drain (source doesnt matter) (node 1) and gate and giving vcc ,now connecting node 1 with the source of a enhancement nmos trans and then...

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