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Recent content by kapil_vlsi1

  1. kapil_vlsi1

    Regions in floorplan

    Regions are ones where cells of other modules are allowed in the designated area whereas fence are ones other module cells are not allowed inside the designated area. So, if you know the meanings of hard and soft blockages/macros you can understand the meanings of these terms... hard_region...
  2. kapil_vlsi1

    Regions in floorplan

    Regions are basically created to make sure the cells of the same hierarchy, and connectivity through flylines are placed inside the regions so that the timing does not get impacted. Advantage is that cells of the same hierarchy are placed together in a cluster/region thereby reducing timing...
  3. kapil_vlsi1

    [SOLVED] floorplan effective techniques

    This is the slide for calculation the width of the straps and core ring width.
  4. kapil_vlsi1

    cells are not honoring regions even after using setPlaceMode -forceFenceRegion true

    Its working but the main reason why we are giving is to legalize placement. Still some overlaps in standard cell after refine place and setPlaceMode -forceFenceRegion true -hardFence true -honorSoftBlockage true or do we have to fix it manually.
  5. kapil_vlsi1

    cells are not honoring regions even after using setPlaceMode -forceFenceRegion true

    cells are not honoring regions even after using setPlaceMode -forceFenceRegion true in Encounter. Is there a way in encounter how we can make the tool honor regions. Please help.
  6. kapil_vlsi1

    Script to find out the mid point of coordinates using TCL in Encounter

    Script to find out the mid point of coordinates using TCL in Encounter. Does anybody know how to wirite TCL script to find out the mid point of coordinates in Encounter.
  7. kapil_vlsi1

    How to balance the skew if we have two clocks domains in a design

    How to balance the skew if we have two clocks domains in a design. Please help
  8. kapil_vlsi1

    Corner and Scenario?

    Corner analysis is analysis of different PVT conditions like slow, fast and typical corners and Scenario analysis or Mode Analysis is Functional mode or Test mode analysis.
  9. kapil_vlsi1

    How to calculate the width of macro ring

    How to calculate the width of macro ring
  10. kapil_vlsi1

    Local Skew & Global Skew

    what is global skew Significance of Global Skew is it finds out the delay of the clock tree in such a way that it removes the setup violation as well as Hold violation. In this context, we have to use skew balancing to get the required slack. Hope this helps...
  11. kapil_vlsi1

    Local Skew & Global Skew

    local skew global skew Local Skew : Source and Destination flop insertion delay is called local skew. Global Skew : Max insertion delay minus Min Insertion Delay is called Global Skew.
  12. kapil_vlsi1

    Significance of Global Skew

    skew signficance Significance of Global Skew is one need not perform CTO as Setup and Hold Check is already done as Useful Skew optmizises in such a way that there is no setup violations. For more info: **broken link removed**
  13. kapil_vlsi1

    Why high fanout of test clock will result in IR drop issue?

    Re: what's IR drop? wht i mean to say if width of the clock net is more ..resistance is also more... so Voltage drop is also more. V = IR. I think so.. correct me if i am wrong... but as u said IR Drop is due to power grid so we perform Power Network Analysis and so on... Other ways of...
  14. kapil_vlsi1

    Reg Rectilinear floorplan and Rectangular Floorplan

    rectangle floor plan Hi all, y is rectangular floorplan is more used than rectilinear floorplan. wht is the reason. also wht r the pro and cons of recitilinear and rectangular floorplan. Sorry for the incorrect question. This is the question.
  15. kapil_vlsi1

    Why high fanout of test clock will result in IR drop issue?

    Re: what's IR drop? it depends upon the width of clock net where there would be IR Drop if the Width of clock net plays a important role. Its important in calculatiing optimal IR Drop or Voltage drop across the VDD. Fanout is nothing but the drive strength so more the fanout more the voltage drop.

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