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Can you tell me, the specification for ur ADC to be designed. Because for digital blocks, I have used two phase non overlapping clock, ring counter, shift resistor and logic gates combination.
So, If you could make more clear on your object, hopefully, I would be able to help you....
Thanks...
Dear friends!
Can someone refer good study material for selection of buck regulator architecture. I have to design it for input (1.6-4.2) and regulated output voltage of (1.2-1.8) and max output current is 60mA.
Waiting for your kind response.
Thanks and regards,
KKR
Thnx but I would try the same u told. But can you tell how I will calculate the ID0 i mean characterstics current. You know very less has benn given for Subthreshold design in Books.
Regards
Kapil
Added after 47 seconds:
Thanx Jimito and Overlems!
Added after 5 minutes:
Jimito, I don't...
Hi all,
Can sombody tell me how to calculate the Id0 and slope factor "n" so that I can obtain the W/L ratio for MOS working in subthreshold operation. The equation is as followes:
Id=Id0*(W/L)*exp(Vbe/nVT);
Id0 is characteristics current and "n" is slope factor. Is it the way to obtain the...
Dear Friends, I am designing 10-bit SAR ADC. The blocks comparator, DAC has been completed.
But I am fully unaware of, how to design the digital control circuit.
Even I have tried with shift register, ring counter, D-FF , Non overlapping clock and gates.
But couldn't succeeded. Even I am getting...
systematic offset sigma
I have some query!
I have done simulation of two stage CMOS op-amp for input offset voltage. My op-amp is PMOS input diff pair.
What I did is that, I connected one input negative terminal to output. Now at second positive input terminal I applied a dc voltage of 1V. My...
monte carlo simulation cadence
Dear members!
I am using Virtuoso ADE XL(7.1.2)Schematic editor & facing lot of problems in running the simulations like corner and Monte-Carlo.Basically and not getting the proper documentation for these problem.I min i want to get some examples in which i can...
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