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Hi. I', using xilinx Ultrascale+ FPGA
I am referring to application notes provided by xilinx.
I am going to use the reference code provided in xapp1315.
In this reference code, an external clock of 100 MHz enters to FPGA, passes IBUFDS_DIFF_OUT, and then goes to idelaye3.
I am going to...
Hi.
I'm using ultrasclae+ . I want to use the xapp1315 in my design for 1:7 deserialization.
In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS.
But in my design, there are many other logics, so xapp1315 design can not be top file.
The main problem is...
Thanks for your reply.
Yes.
As you told, the ADC has a clock output.
This clock is 50MHz ( 1/2 frame clock which was aligned with data).
For some reason I have to use 100MHz clock (still aligned with data) in FPGA.
This is why i want to make 100MHz clock without phase difference.
I also...
Hi,
I'm going to process the output of adc in FPGA.
There is 50MHz clock output of ADC ( CLK1) which is aligned with data.
I want to make 100MHz clock(CLK2) from CLK1 without any phase difference.
The CLK2 still wants to be aligned with ADC data.
Which method is most suitable to make...
Hi.
I am using 12bit ADC, Texas Instruments ADS5295.
Table 20 on page 75 of the manual shows that ads5295 supports 14x serialization and has to be used with digital processing function (such as averaging and decimation filter).
However, there is only a timing diagram for 10x and 12x...
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