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Recent content by kanagavel_docs

  1. K

    Domotics product Ideas

    Hi, We are planning to implement home automation. The idea has been captured in the attached. I want to add more features. For that I am expecting comments/suggestions from edaboard members also. If anyone interest to implement the same can cotact me. Thanks & Regards.
  2. K

    FPGA final year project for electronic engineering

    electronics communication final year projects For FPGA related projects contact me on kanagavel_docs(at)yahoo.com
  3. K

    Looking for academic projects?

    yes we can.First we will do a matlab model for this one and then we can develop the RTL coding.
  4. K

    Looking for academic projects?

    yes, But only in VLSI/DSP.
  5. K

    Looking for academic projects?

    academic projects Hi, please contact me if you want any academic projects.
  6. K

    why we need clock transtion(edge triggering) for flip-flop

    whats the need of clock pulse in flip-flop Hi, If we are not using the edges, whenever the input value changes output also change accrdingly. Because of this we will get erroneous values before settling in actual value. It will make unnecessary switching and power loss. So we are narrowing the...
  7. K

    Looking for help with implementing I2C in FPGA board

    Re: I2c in FPGA HI, What kind of help you need? Do you any SOC design to integrate with that? Regards, Kanags
  8. K

    Which type of synchronizer is best and why?

    Hi All, What are the types of synchronizers and how we can choose the types of synchronizer and what are the limitations ? Thanks, Kanags
  9. K

    Implementing a Latch using a Flip Flop ???

    Hi, Please find the circuit. Correct me if I am worng. Regards, Kanagavel. S
  10. K

    Is there anybody used the Modelsim to simulate?

    Hi, You need to add some files from modelsim library. Add 220model.v and apex20k_atoms.v(if you are using apex20k chip) and altera_mf.v files. It will work. Regards, Kanags Added after 2 minutes: Please take the library files from quartus\eda\sim_lib\ folder...
  11. K

    Detect number of bit change in one clock cycle

    Hi, Please find the simple flow with verilog code assign no_of_change = data_dly ^ data_in; always @(posedge clk) data_dly <= data_in; for (i = 0; i=3; i = i+1) //it will implement the combinational logic count = count + data_in[i]; this count will give you the number of changes...
  12. K

    Why this Verilog coding used in testbench is wrong?

    Re: About verilog coding Hi, This always block is sensitive to a, b, c inputs only. So tough to capture the rising edge of clock. If the clock rise and any one of the input change happens at the same time only the execution will move from this statement. So, add clock in the sensitive list and...
  13. K

    Why this Verilog coding used in testbench is wrong?

    Re: About verilog coding Hi, Plese describe your requirement... Kanags
  14. K

    Our team offers the development services: SW/HW design

    Hi, Please tell more about you...
  15. K

    How to handle the interrupt processes in AHB?

    Hi, Is there any dedicated pin for Interrupt? If it is not how we can handle the interrupt related processes? Thanks in advance. Regards, Kanags

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