Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
worst neg slack
Worst Negative Path(WNS) points to the path having the maximum negative slack.
Total Negative Slack(TNS) gives the sum of all the negative slacks in the design.
From the value of TNS, we can know the severity of the slack in total design and whether to proceed or not with the...
Re: Hot Electron effect
1)This is hot electron effect is due to the shrinking of technology. If we go on reducing the length of the gate,the electric field at the drain of the transistor increases(for a fixed drain voltage).
2)The field may become so high that electrons are imparted with...
Re: CTS
Hi
May be the top most layer specified in the .cts file exceeds the Maximum layer number and also check the tcl script file to see whether the top most layer is within the limit or not.
In the .cts file, the clockroot pin may be an output port but has been included in the constraints...
Re: setup violation
Actually, If a chip has setup violations, it is not considered as COMPLETED.
A completed chip cannot have any violations.
To Decrease the setup violations,
Insert the buffers. As delay is proportional to the square of the length of the net, inserting the buffers will...
Re: power analysis
VoltageStorm Professional Edition performs flat and hierarchical power-grid analysis and
signoff of cell-based designs, such as custom integrated circuits (ICs), application-specific
integrated circuits (ASICs), and systems-on-a-chip (SoC). It is one of the Cadence signoff...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
