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Recent content by k621219

  1. K

    [Recommend the stackup and layers for HDI PCB ]

    Thank so much for your advice. Now I have price problem. I have received several quotations for HDI PCB fabrication. - Board size: 40 mm x 40mm - Quantity : 4 - Layer : 12 - Build-up PCB (HDI PCB): 3-6-3 (12 layers) - Blind via: L1-L2, L2-L3, L3-L4, L9-L10-, L10-L11, L11-L12 -...
  2. K

    [Recommend the stackup and layers for HDI PCB ]

    [Recommend the stackup and layers for HDI PCB ] I am designing the PCB for BGAs at double side. **broken link removed** I think that it will need to use HDI PCB. It is first time to do HDI PCB design. It is difficult to decide the layers and stackup. I am considering about the following...
  3. K

    How much have frequency in Full HD progressive 1frames?

    Please refer to the following link. https://www.itu.int/dms_pubrec/itu-r/rec/bt/R-REC-BT.709-4-200003-S!!PDF-E.pdf https://www.itu.int/dms_pubrec/itu-r/rec/bt/R-REC-BT.709-3-199802-S!!PDF-E.pdf
  4. K

    vhdl code for division of two fixed point numbers

    You can find some VHDL code from "Circuit Design with VHDL Volnei A. Pedroni".
  5. K

    What kind of PC/Workstation do you use for ASIC or FPGA design works ?

    What kind of PC/Workstation do you use for ASIC or FPGA design works ? I have used dell Vostro 430 for FPGA design( RTL logic simulation, synthesis, FPGA implementation) - i7-860(2.8G) - 8G RAM - 1T HDD Now I am considering to upgrade PC to speed up my work. So I would like to know what kind...
  6. K

    In IP business, what kind of code is provided to customer ?

    I have developed and provided camera ISP core IP. I have provided the obfuscated RTL code to customer. But there are some customer to want original RTL source code. I have provided the RTL code by obfuscation tool to protect our IP core. In IP business, what kind of code is provided to...
  7. K

    Double rate registor for DQ and DQS DDR in SDRAM controller ?

    ASIC Double rate register for DQ and DQS DDR in SDRAM controller ? I am developing DDR2 SDRAM controller. In FPGA, I used a double rate register. In ASIC, What kind of logic do I need to use for double rate register?
  8. K

    ASIC double data rate (DDR) register like ODDR/IDDR of Xilinx FPGA?

    I am using ODDR and IDDR at Xilinx for DDR2 SDRAM controller. ASIC library has the data rate (DDR) register similar to ODDR/IDDR ?
  9. K

    IP business, How to protect FPGA configuration PROM.

    Hi kvingle, You are right. User can't integrate his own into bitstream. This is another business. Exactly not IP business, I would like to sell the IC instead of IP core because IP core price is too high to small company. Anyway, It is a little problem that user can't integrate their own logic...
  10. K

    IP business, How to protect FPGA configuration PROM.

    I am developing IP core. Generally, IP core price is too expensive to small company. So I would like to sell the FPGA configuration PROM with bitstream of my IP core. But PROM copy protection is a problem. I want to know how to protect IP core and PROM copy. If it is possible, I could sell the...

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