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Recent content by jyothia

  1. J

    cadence QRC extraction script

    Can any body help me with QRC extraction script. I want to execute QRC as an independent tool. An example script with an explanation will be good enough.
  2. J

    Static Power vs Dynamic Power

    Like to at what PVT Static and Dynamic IR analysis should be done and WHY ?
  3. J

    Compairing RC value {Synthesis & Layout}

    Thanks for your i/p. But the concern now is how I can generate a spef after synthesis. Is there a way..if so plz let me know. Thanks once again for the help.
  4. J

    Compairing RC value {Synthesis & Layout}

    Can you tell me the procedure how we can execute it..any website
  5. J

    How to decide on the EM-corner {PVT} for POWER/Signal EM checks?

    Hi, Just wanted to know how we decide on the EM-corner {PVT} for POWER/Signal EM checks.
  6. J

    Compairing RC value {Synthesis & Layout}

    Hi, We are using a wire load model at the Synthesis stage {2k_6LM}, but after final layout we have different RC value. We need to compare the two RC value one during synthesis and one after extraction at final layout stage. Can you please help me how to proceed about this. What sequence of...
  7. J

    Setup-Slack : Divide by 2 ckt

    How we can estimate setup-slack for a divide-by 2 ckt...Is there will be a valid timing path between the D and the Q o/p of the same.
  8. J

    X-talk is dependent on frequency?

    noise xtalk Hi, Like to know whether the X-talk Noise and delay is dependent on freq. If anybody can explain it with mathematical equation, it will be very good.
  9. J

    CTS : Balancing to clock feeding to a MUX

    Hi, That is true that we need to balance CLK1,CLK2,CLK3...But do we need to balance test-clk also along with the other clk (clk1,clk2..) If we need to balance then how can we go about it...
  10. J

    CTS : Balancing to clock feeding to a MUX

    Hi, Please find attached the scenario.
  11. J

    CTS : Balancing to clock feeding to a MUX

    Hi, Suppose from PLL o/p we have many clock comming out and each clock is going to a 2x1 MUX along with a TEST clock. My question is how we go about balancing in this clock....
  12. J

    Resistance requirement for ADPLL

    hi , For many ADPLL design we have resistance requirement other than the power. Where as for Macros we generally check for the requied IR-Drop. Can anyone tell me the reason.
  13. J

    reg:Integration of Analog and Digital module in the same Die

    Hi , I have a basic quey. In a SoC we have both Digital and Analog blocks. So is it possible to have different process of Analog block and digital blocks.If so then how and if not the why ? Also I'm bit curious to know how Analog and Digital block integrated in the same die.
  14. J

    reg: Clock Tree synthesis

    clock tree synthesis inverted clock Hi, Query1: I have done CTS and after that I have got two report one clock skew report and one timing report. Now there are some clock path group whose Global skew is bad and also I can also see timing violation for the same clock path group is quite high...
  15. J

    reg: Establishing the Clock Tree

    yes
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