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Recent content by josephine1234

  1. J

    How to get real time instances of an ECG signal

    Re: How to get real time instances of an ecg signal to a simulation test bench - - - Updated - - - i did the processing for a single input..now I am struggling to apply the same for continuous inputs (real time) and to store it.. can anyone help me with this.. thanks in advance..
  2. J

    How to get real time instances of an ECG signal

    How to get real time instances of an ecg signal how to get real time instances of an ecg signal as input in vlsi codes
  3. J

    ppg database regarding

    can anyone send me the ppg database ?.. I've gone through the internet and all data are in matlab format.. i need it to work with verilog..could anyone help me ?..thanks in advance..
  4. J

    Regarding Verilog codes

    thats the real to fixed point conversion codes
  5. J

    Coding help in Verilog

    ive already gone through the site u mentioned.. thanks!
  6. J

    Coding help in Verilog

    how do i include any file in the test bench?
  7. J

    Regarding Verilog codes

    module fix(x,z,x1 ); input signed [4:0]x; output z; output signed[14:0]x1; localparam signed [11:0] y = 12'b100000000000; reg [14:0]z; always @* begin z=x*y; end // selecting msb reg z1; always @* begin z1=x[4]; end // to check if number is positive or negative reg [14:0]x1; always...
  8. J

    Coding help in Verilog

    where must i include the file required for readmemb command in verilog
  9. J

    coding help needed in verilog

    how do i get samples of a signal
  10. J

    coding help needed in verilog

    what is moving average filter? how do i get samples of a signal in verilog?
  11. J

    Error in verilog code

    Re: error in verilog code ive converted into a for loop... initially i used for and ended with many errors..so i decided to unroll them... and as i was rushing up i dint realize my mistake and posted it in here so that u people could help me... thanku anyways..
  12. J

    Error in verilog code

    the code is : reg [63:0]sum1,sum2; initial begin sum1=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5]...
  13. J

    FIR band pass filter using verilog

    Re: fir band pass filter using verilog What FPGA can be used to interface with an ADC? how should I interface FPGA with a circuit that produces analog input?Does Fpga give digital output?
  14. J

    FIR band pass filter using verilog

    Re: fir band pass filter using verilog as i am new to verilog i find it hard to code..
  15. J

    FIR band pass filter using verilog

    can i pls get the codes of fir bandpass filter using VERILOG with a bandwidth of 6-18 hz and 360 as sampling frequency.. kindly help me with the same...
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