Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by joharali

  1. J

    Is it possible that lvs passes but ERC/Softcheck fails

    Hi, Can you help me out with what type of possible violation test cases I can create to examine this type of scenarios ?
  2. J

    Is it possible that lvs passes but ERC/Softcheck fails

    Is it possible that lvs passes but ERC/Softcheck fails. If yes in what type of cases this happens ? Thanks in Advance , Johar.
  3. J

    Format of CDL netlist

    Can someone explain me the format of a CDL netlist in detail. Does each and every subckt name in the cdl netlist represent a cell/macro reference name in the Block. If yes I am observing couple of subckt names (like .SUBCKT ICV_74) which are not found in my tile as cell/macro ref names. How do...
See more

Part and Inventory Search

Back
Top