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does anyone know what is the frequency of operation in variable gain amplifier under nb-iot applications. The VGA is after mixer and no study is conducted about this topic.
Thank you for your reply, sir. Can you recommend any book or reference for designing a VGA? Actually, this VGA is for the transceiver and I'm a newbie in RF design.
Good day Everyone!
I'm currently studying about dual band variable gain amplifier for wifi which means the 2.4GHz and 5GHz. This block is part of the AGC. However, I believe that this frequency will be down-converted since this block is after the mixer in the receiver. I don't know what is the...
Hi!
Can anyone suggest a good topic for current mode dc-dc buck converter? It would be nice. Or a good book reeference for this topic. Or discussions of different architectures of current mode buck converter. Advantages and disadvantages.
Hi All,
I am looking for a tcl script to run my standard cells in batchmode. I am using hercules and I just want to verify whether there are errors for my standard cells.
Thanks
Good Day!
How do I perform formal equivalence checking if one of my module is set to don't touch since I instantiated directly a standard cell on it. When I add this module to Reference Tab, it cannot be link to the top module. Can you please tell me the proper step. Thanks a lot.
Hi,
The picture I have attached is an asynchronous code. However, my library does not contain asynchronous reset. How do I modify my code into synchronous preserving it's functionality. Please help I'm newbie in RTL coding
Thanks
Hello everyone,
I had run a formality test in my design. It has too many unverified points and also had some failing points. I look at my "check_design" report, it has no errors but there were a lot warnings. I attached the screenshot of my results both in formality and synthesis report. How...
Hello everyone
I have run DC. There were no error in my reports but there were a lot of warnings. I have attached some of the screenshots in my "check_design" report. Is this the reason why my formality test failed? If so, how can I reduced or eliminate the problem.
Hi All!
Yes I am talking about mapping it into my technology file. I have already read the datasheet of my library, it contains no async reset FF. What do I need to do? is it to make a new standard cell library or to revise my RTL code?
Hi! May I know if what are the verilog code that are not synthesizable. It can be converted into the generic lib but there are no equivalent cell in my target library. For example:
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