Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Can you explain the difference between bc-wc and OCV in
OCV (On Chip Variation) tries to take care of local variations within a chip, while the different corners take cares of the whole range of variations from chip to chip. You usually use OCV for 65nm and smaller process nodes.
As...
I believe that Var1 will be assigned bit 0 of the 8 bit ASCII value of the character -. The simulator or the synth. tool should give a warning about truncating.
Re: DC -topo Error
I believe this means that the utilization is more than 100%, so the die area is too small.
Run DC without the physical constraints and check what the netlist area is. If the area is bigger than your die area constraint, the you have to revisit your floorplan.
Also try...
Re: wlm vs sdf
In the old days DC was unware of cell placement, and wire load model (WLM) was used to estimate the netdelay. The WLM is based on the net fanout, and each standard cell library contained some WLMs to choose from.
Now DC is placement aware, running the tool in topographical mode...
Hi,
DC has the capability to do a virutal layout, and with hints about the layout and correct constraints DC should be within 5% from e.g. IC Compiler.
To get accurate reports from Primetime you need to give the tool information like RC data from StarRC and a netlist with clock tree inserted...
Verilog flip-flop:
reg d;
wire load, value;
always @(posedge clk)
begin
if (load)
begin
d<=value;
end
end
The flop will be loaded at rising edge when load is 1. Without clock gating this will ble implemented as a 2-1 mux in front of the flop. The load signal chooses if d (fed back)...
Re: finding critical paths in design vision
Yes, you can find your critical paths using Design Vision. Check your manual for report_timing. report_timing -max_path 10 will report the 10 worst paths per timing group.
Internal power is power dissipated within the boundary of a cell. During switching, a circuit dissipates internal power by the charging or discharging of any existing capacitances internal to the cell. Internal power includes power dissipated by a momentary short circuit between the P and N...
Re: The following generated clock has no path to its masterc
What I believe is that there exists no timing arcs between the two clocks, hence the warning. I also believe that you should use the create_generated_clock command to make a second clock.
In FPGA you would use a primitive to...
Re: LVDS I/O in ASICs
LVDS is pretty analog stuff, and you are _usually_ not able to mix analog and digital design when doing layout. I believe LVDS modules can be bought from companies designing analog I/O.
What is the more practical solution is to use a simulation model for LVDS when you...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
