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Recent content by jobnom99

  1. J

    gather information of code coverage tools

    RTL code coverage Tool 1. TransEDA Vnavigator ==> I have good experience for GUI interface of code Coverage but, we have to invoke Cadnece simulator ( Nc-sim or verilog-XL). you need to waste time for link to cadence tool. but, result is good and gui...
  2. J

    The definition of synthesis process

    Re: synthesis ? if you have simulated RTL code , and you decide to FPGA target devices. in normal case , there is 2 ways to synthesis. 1. FPGA SW provided FPGA Vendor for example , you can use max2plus or quatus of altera , if you use Altera. you cans...
  3. J

    Who will do ATPG in Asic design team ?

    atpg pattern there are some tools for atpg. but, alomost pepple use as bellows tool. 1. synopsys test_compiler ( until 2001.08 version) Synopysys testgen Synopsys TetraMax ( now ) 2. Syntest 3. veritest 4. mentor DFT architecture
  4. J

    DFT workflow in the ASIC design

    tetramax boundary scan This is My synopsys DFT flow 1. HDL design considering Testing ==> you can check Synopsys RTL TESTDRC check with DFT compiler ==> Memory : Memory BIST logic insertion 2. Synthesis considering Scan : DC Compiler ==> compile -scan ( pre_compiled with scan)...
  5. J

    good PLL sildes to download

    thank you thank you for good data. No "thank you"s on Elektroda! **broken link removed**
  6. J

    Is there a ATPG tool for Windows?

    TetraMax from 2002.05 version, synopsys only support TetraMax as ATPG tool. so, if you have ATPG vector in synopsys DFT compiler , you have to buy TetraMax license. until 2001.08 version, synopsys support "create_test_patterns" in DFT_compiler. but now this command disappear and...
  7. J

    I am getting MAD with these Synthesis result.Can anyone help

    aoi31x1 Dear... gate count is based on ND2 gate to Unit cell. but, according to vendor , unit value is some different. for example , UMC/FTC ND2 = 2.7 UMC/GCI ND2 = 64.8 if total gate is 10000 UMC/FTC = 10000 / 2.7...
  8. J

    What is a good starting point for FPGA design?

    FPGA FPGA is dependent on FPGA Vendor normally, people use major FPGA vendor 1. Xilinx 2. ALTERA 3. ACTEL and their vendor have their own tool. Xilinx => foundation 5.1i , foundation 4.1i altera => Quarus 2.1 , max2plus 10.1 actel => Libero 2.1 sometimes , 3-rd...
  9. J

    Some Good Stuff for Physical Synthesis

    comparation DC + Astro and PC + Astro good for you
  10. J

    Advanced Chip Synthesis ready made Scripts, and Flow Tutori

    ACS 2002.05 sold This Synopsys ACS 2002.05 sold CD. according to my experience , ACS is very powerful in high gate design. especially, timing constraints. becasue acs use budget_shell , now 2002.05 use design_compiler time budget but in earlier version , use the primetime's budget shell. and...
  11. J

    Description of Physical Compiler tool

    Physical compiler Dear.. thank you for your good suggstion. first , physical compiler is synopsys commercial tool. Physical Compiler is a block-level timing convergence tool that combines proprietary synthesis, placement, and static timing analysis tools. These tools have a common...
  12. J

    psyn: physical compiler sold

    according to some reqeust... I hope this help you.
  13. J

    psyn: phycical compiler advanced

    hope to helo you....
  14. J

    syn physical compiler introduction

    This is physical compiler intro presentation. hope to helpful...

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