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Recent content by jleslie48

  1. J

    dc-dc booster, how do I ensure I don't draw too much amperage.

    Yes, in a battery system, reducing effciency is a bad thing, and also any heat generation is counter productive. So continuing with the thought experiment (I concede the KISS it solution is simply an in-line fuse,): 1) which of the links are you referring to for the "shown transistor current...
  2. J

    dc-dc booster, how do I ensure I don't draw too much amperage.

    thank you for your response, and yes over-engineering is something I am very guilty of in the past ;) The fuse is definitely a good idea. I'd still like an explanation as to why a resistor in-line would not be an effective amperage limiting solution.
  3. J

    dc-dc booster, how do I ensure I don't draw too much amperage.

    I have a bunch of 24v dc fans I want to power from a marine battery at 12v for an rv. each fan draws 110ma I wired them in parallel, so my load is 440ma (I think) Now If I power this directly from the 12v, the fans run slow, so I bought: **broken link removed** 150W DC-DC Boost Converter...
  4. J

    RS-232 Receiver and Transmitter Design in VHDL

    transmit ascii via rs232 verilog look here: https://academic.csuohio.edu/chu_p/rtl/index.html
  5. J

    RS-232 Receiver and Transmitter Design in VHDL

    vhdl uart receive project I have no idea what "that" is in the above. You must avoid using pronouns in online discussions, and fully label all nouns. "There is a version of <whatever your referring to clarified goes here>, or comething like <need a reference here to> in verilog too ?"
  6. J

    RS-232 Receiver and Transmitter Design in VHDL

    vhdl rs232 link module here is the latest of my build: ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" LOC = "AD10";> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" LOC = "AE8";> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_RTS_IN" LOC = "AK8";>...
  7. J

    RS-232 Receiver and Transmitter Design in VHDL

    verilog code for rs232 Here's my version of a blog on how to get this UART working. Its a complete backup of my workspace on the project in its natural tree form, and there is also a zip file of the project if you want to download it in one fail swoop (3mb) the backup is here...
  8. J

    RS-232 Receiver and Transmitter Design in VHDL

    vhdl uart receiver LOL!!! I just picked up a copy of the whole book, hard copy and even the pdf for searching. It's a great book. I'm going through it now (I'm scared to lock and load, and just run the RS232 example.) This is great stuff. Its all clicking now, this is exactly what I...
  9. J

    RS-232 Receiver and Transmitter Design in VHDL

    rs-232 vhdl+fpga Ok, I'm going through this chapter. Its very well written, and I've even gone ahead and ordered the book its from. Quick question. the article introduces on book in section 7.2.4 A flag FF. What is a Flag FF? does the FF stand for flip flop? I can't find a definition...
  10. J

    RS-232 Receiver and Transmitter Design in VHDL

    rs 232 vhdl OH THANK YOU!!!! I just downloaded it I can't wait to try it out. I'll give a full report shortly.
  11. J

    RS-232 Receiver and Transmitter Design in VHDL

    vhdl rs232 receiver Quote:" Another, more basic UART project from Quote: but i didnt find anything matches my likings You may rather like to design your own UART, it isn't that difficult and instructive anyway." Hello all, I just surfed in looking for a VHDL tutuorial demonstrating RS232...

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