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Recent content by jinformations

  1. J

    3-bit adder w 4 bit sum; connect to 2 "7 segment" displays

    module Fulladd( input a input b, input cin, output s, output cout ); xor(s, a, b, cin); and(t1, a, b); and(t2, a, cin); and(t3, b, cin); or(cout, t1, t2, t3); endmodule module add3(a2, a1, a0, b2, b1, b0, s2, s1, s0, cout); input a2...
  2. J

    How to show a full adder output on a 7 segment display

    Hello, I am a senior at Indiana State University. My major is Information Technology but I am taking a verilog class to get an intro into it. I created a full adder but I am not sure how to get it to display on a 7 segment display. I tried to do some research but the way some of the coding is...
  3. J

    Creating a system that takes two 3-bit inputs and outputs a 4-bit number

    Hello, I have tried to do some research on my own and trying to implement this on Vivado for a class. My professor is horrible at teaching and I am a IT major and just trying to understand basic verilog but did not know it would be this hard. I am not strong on this subject so please be...
  4. J

    3 bit unsigned adder in behavioral verilog w a 4-bit sum

    Okay thanks! I will try to do some self research before I ask some more questions! I just got stuck with a not so good professor and I am actually a IT major just taking this to learn some verilog so I am not strong in this subject. I know basic verilog just not behavioral and my professor...
  5. J

    3 bit unsigned adder in behavioral verilog w a 4-bit sum

    I need help creating verilog that takes two, 3-bit unsigned integers as input, adds those two integers together to produce a 4-bit sum, and displays that sum on 7-segment display. I need it to be in behavioral verilog. Can anyone please help me with this? I am going to be displaying it on a...
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