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Recent content by jincyjohnson

  1. J

    fpga implementation of circuits having clock

    The clock divider code is as follows [/CODE]library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity c1 is port ( CLKin: in std_logic; reset: in std_logic; CLKout: out std_logic); end c1; architecture arch of c1 is...
  2. J

    fpga implementation of circuits having clock

    i want to giv a frequency of 1Hz from 50 MHZ. can u please giv the code. if the input clock 0f 50 MHz is given as clk1 and output of 1 Hz is denoted as clk2, which clock is used in main program - - - Updated - - - i didnt connect to the kit. I think the clock frequency can be changed by clock...
  3. J

    fpga implementation of circuits having clock

    I am using vhdl coding for a sequential circuit. The implementation will be done using spartan 3EXc3s500E. If we use the clock frequency of the fpga kit, we cant view the pattern change during each cycle, since the clock frequency of the kit is 50 MHz. So how can we view the output at each clock...
  4. J

    fpga implementation of circuits having clock

    for circuits having clock, whether we have to use a clock divider for imlementing the circuit in fpga.if so, can u plz explain.
  5. J

    fpga implementation of circuits having clock

    if we want get a pattern that is changed in ach clock cycle, how can we run in spartan 3E fpga kit. plz reply
  6. J

    accumulator based pattern generation

    what is the method of generating test patterns in accumulator based weighted pattern generator. What is the use of session counter
  7. J

    how to write the ucf file in xilinx for array variables

    totally it generates 16 number of 8 bit vectors. So it cannot be done it spartan 3E as it does not contain the enough number of input pins. can u suggest another option plz.
  8. J

    how to write the ucf file in xilinx for array variables

    the pattern is generated as follows (example only) chain1 [11110000 11111000------] chain2 [11000000 11100000-----] chain3 [11100000 11100000---] chain4 [10101110 11101110-----] here each vector in a chian are of 8 bts. i didn't get NET chain1[0][0] LOC "p23"--first bit of first vector NET...
  9. J

    how to write the ucf file in xilinx for array variables

    The main entity is as follows library ieee; use ieee.std_logic_1164.all; Package my_pack1 is type arr1 is array(0 to 15) of std_logic_vector(0 to 7); type arr2 is array(0 to 31) of std_logic_vector(0 to 7); end package; library...
  10. J

    how to write the ucf file in xilinx for array variables

    in the main program i have some output variables which are declared as array. ex: chain1, chain2:out array Each bvariable stores 7 bits.ie: chain[0] to chain [7] and similarly for chain2. If we use std_logic_vector , in ucf file we can write it as NET "chain<0>" LOC "p23" NET "chain<1>" LOC...
  11. J

    gate count in the synthesis report in xilinx

    can we manually calculate the gate count
  12. J

    gate count in the synthesis report in xilinx

    how can we compare the area with an existing system
  13. J

    gate count in the synthesis report in xilinx

    During synthesis in xilinx, i got number of slices,slics flip flop, 4 input LUT's, bonded IOB's GClk's. How can i get the number of gates. plz reply
  14. J

    how to write the ucf for clock signal

    how to write the ucf for clock signal if there are 2 clock signals for spartan 3E fpga kit. the pin number of one clock is p122. How can the other clock signal can be included. plz reply
  15. J

    Expanded RTL view and technology view in xilinx

    How to view the Expanded RTL view and technology view in xilinx

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