Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
decimation and interpolation/
When creating interpolation simulink model,
I got two different result from these two models.
Assume I want to create upsampling 2x system.
The first system, upsampling 2x then halfband FIR filtering.
The second system, only use one polyphase IIR filter.
I think...
The concept of the tracebakc is similare to "sliding window".
That's to say,
Assume constraint length=7,buffer for 64 bits.
Some textbooks said that 5 times constraint length is good enough for traceback to reach some reasonable BER.
So u first traceback 35 stages and then find a merge point...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.