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Recent content by jimmy_tag

  1. J

    Job for IC Design Frontend(India)

    Hello nick703, I tried to apply in some companies but most of them wants experience, how can we get experience if we dont get work.
  2. J

    Job for IC Design Frontend(India)

    I am Prasad Pandit, BE in Electronics Engineering. I have worked on lots of FPGA and embedded system projects for foreign university students as well as some small companies. I have 3 years of practical experience working as Freelancer in this field. I started a blog vhdlcodes.com to help...
  3. J

    Nios ii de2 sof problem

    I guess you might have selected Active serial programmer in your Quartus. select jtag and burn the code it will work.
  4. J

    VHDL code problem design 8bit wide 2-to-1 multiplexer

    Corrected myself.. Thanks..
  5. J

    VHDL code problem design 8bit wide 2-to-1 multiplexer

    as you used SW() x() and y() to assign their values so you wipl have to add x y n SW in sensetivity list of process..
  6. J

    I'm looking for a FPGA project

    For simple projects you can visit this site: All About VHDL Codes, PCB Designing and AVR
  7. J

    Floating point in VHDL and FPGA

    Hi the VHDL-2008 revision now provides Floating point calculations library from ieee both testbench and for Synthesis. I have attached a zip which contains new libraries.
  8. J

    clock division with vhdl??

    The code on my site is Synthesizable. And it gives 100% output. You should try it first. And about clock enable, u can directly add signal to my code..
  9. J

    generating a 1 clk cycle pulse

    My apologises to FvM. I think i was too exited. I shouldnt have done that. I made corrections now. ---------- Post added at 20:18 ---------- Previous post was at 20:09 ---------- I think the main question actually is incomplete.
  10. J

    display 2digit number in 7-segment

    yup, he only wants to show the o/p on seven seg ..:-?
  11. J

    display 2digit number in 7-segment

    you should search for bcd to seven seg decoder IC and interface it to seven seg display then.
  12. J

    generating a 1 clk cycle pulse

    you better compile it yourself first then talk. And yes, till now my codes are working perfectly using this condition. And Who said its a Asynchronous Reset, did I mentioned that?? I just initialized signal with name 'rst', it dosent mean its a reset signal. You should read the complete code...
  13. J

    divide a number in vhdl

    Its also one of the problem... u cant assign 5-bit signal to 3-bit signal. and its obvious you should use numeric_std. I agree with FvM about the libraries support.
  14. J

    Multiplexer Design Error

    make these changes: --add signal s4 begin s1<=Din1;s2<=Din2;s3<=Din3;s4<=Din2; with sel select Dout<=s1 when "01", s2 when "00" ,--remove Dout from these lines s3 when "10", s4 when "11", 'X' when others;
  15. J

    Simple synchronisng problem.

    just set the flag for each block.
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