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Recent content by jimjim2k

  1. J

    How to execute feko in a linux machine.

    Re: FEKO execution in Linux Hi The performance and hardware configuration gains that performance are my interest to know. tnx
  2. J

    [SOLVED] power compiler standard cell library (.db)

    Hi I think there is another approach too: Generate the memory with Memory compiler and actually use it in your power estimation. tnx
  3. J

    statements in verilog file

    Remember: compiler directives are starting with backquote so it is correct to write `define NTC 1 `define RECREM 1 `define setuphold 1 tnx
  4. J

    UPF is synthesizable or not

    May you please show sample example? tnx tnx
  5. J

    How to execute feko in a linux machine.

    Re: FEKO execution in Linux Hi Does someone has experiments on parallel FEKO? tnx
  6. J

    Cadence CAD Tutorial - website link to share

    Hi This is also good link: **broken link removed** tnx
  7. J

    The best CAD for electrical drawings

    Still Razavi's is the finest.
  8. J

    Best know SAR ADC design

    I need a comparison with FOM for SA-ADC
  9. J

    What is the most stable LINUX system to run EDA?

    Hi Centos 5.0 or even Centos 4.7 are fine from my view tnx
  10. J

    Transistor Level Layout Tool

    Hi If you want to have IC layout from transistor schematic it is more practical than direct from Verilog to Transistor layout. Tools starting from verilog (RTL, Behavioral, ...) result in gate level logic using sea-of-gates and standard cells. If you want study on schematic to layout...
  11. J

    Modelsim or Silos Which one is better for Verilog Programming

    Hi modelsim is the defacto of HDL world. Good and easy usage, fine waveform viewer and popularity. it also in main stream of tools for mentor graphics. for example mentor Questasim is for verification. tnx
  12. J

    low power comparator design for SAR ADC

    Hi Is it good to use typical op-amp instead of comparator? tnx
  13. J

    VerilogA code for 8b/10b, 64b/66b, 128b/130b encoder/decoders

    Hi if you mean digital decoder then why use from verilog? if you mean analog so what do the numbers mean? tnx
  14. J

    Can the 14bit SAR ADC be realized in a 130nm process without calibration?

    Re: about the SAR ADC Hi Why you use 130n? Is it better than 180n for analog design? tnx
  15. J

    Best know SAR ADC design

    Hi What is the best know SA-ADC design up to now?
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