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Recent content by jiminization

  1. J

    SiliconSmart set_config_opt for individual bus pins

    I am using siliconsmart to generate liberty files. I encountered an error in a cell with multi-bit pins. How do I set a parameter for individual bus pins? I want to set the partial swing of an individual bus pin to another bus pin. Thank you
  2. J

    SiliconSmart Multi-Bit definition

    I am using SiliconSmart to generate liberty file. For a multi-bit pin, I used the pintype parameter so that at the .inst file, the add_pin for the multi-bit will only be one declaration. However, I am encountering a problem during the characterization. Error is undefined parameter or function...
  3. J

    SiliconSmart clock gating cells

    Hi. I am using siliconsmart to generate liberty files. However, I am encountering an error in one of the cells. The tool cannot recognize the cell as clock-gating. Is there any option so as to solve this? Thanks a lot.
  4. J

    SiliconSmart Import Errors

    I am using siliconsmart to generate a liberty file. I am encountering an error during the import command. Error: Functional Recognition for the cell fusecellx8_v1_3v_5b is incomplete I checked everything (netlist, configure.tcl) and could not find the issue. Is there any way to know what...
  5. J

    SiliconSmart pin CK no timing group

    Hi. I am using siliconsmart to generate .lib file. For pin CK of one cell, I cannot generate a timing table. All the other pins have the timing except for pin CK. How can I solve this? Thank you.
  6. J

    SiliconSmart operating condition generated liberty file

    Hi. I am using siliconsmart to generate a liberty file. However, to compare it with the original file, there's an attribute: operating_conditions(typical_op_cond) { process : 1 ; temperature : 25 ; tree_type: balanced_tree; voltage : 1.1 ; } I cannot generate the...
  7. J

    SiliconSmart incorrect instance file generated from import command

    I am using SiliconSmart to create .lib from spice netlist. The netlist that we have is the compilation of different cells (many subckt). When I use the import command, it does not generate the instance file correctly. (It's just a blank file with only the command set_netlist_file and the...
  8. J

    NC verilog schematic to verilog

    I am using the Virtuoso NC-Verilog to convert my schematic to a verilog netlist. However, some of my instance name were renamed. It uses the prefix "Inst_" instead of the name in the schematic. This causes some errors when I apply the sdf in this netlist. How can I retain the name in the...
  9. J

    CADENCE XSIM Default Timescale

    Some of my modules do not have the `timescale directive while some have them. I am simulating it using Cadence Xsim but I did not specify any timescale in the xrun options. What will be the default timescale of those modules?
  10. J

    UVM predictor error: Pending reg items

    I encountered a problem in UVM saying that "[PENDING REG ITEMS] There are 1 incomplete register transactions still pending completion". However, I did not do any access to the said register. How can I solve this?
  11. J

    [SOLVED] UVM Register Model with unknown register address

    Is it possible to create a register model without knowing the address of the registers? There was no way to know the register address. Thanks!
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