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clock inverters v/s clock buffer
Hello All,
I know the significance of clock buffer/inverters over normal buffer/inverters . but I am not able to find the exact difference between clock inverters and clock buffers . I mean how the cts[clock tree synthesis] affects if we use clock inverters...
if there are two combinational ckt between two reg. having more delay.than can we use time borrowing in this case?
please give practical example of this time borowing......
setup slack = Required time - arrival time
if slack is positive then required time is more than arrival time. so, data may be stable before active edge of clock. thus violation is reduced.
if any wire has capacitance is C then capacitive reluctance is (1/(2*pi*f*C));
if any wire has capacitance is L then capacitive reluctance is (2*pi*f*L);
impedence Z= R+ (capacitive reactance - inductive reactance);
if u consider ideal wire, it has no capacitance or inductance.so its impedance is same as resistance.
but for practical wire this is not the case.
wire has some capacitance and inductance.so reactant will change. hence impedance and resistance will be different.
do u mean slack?
it is of two types.....positive or negative.
suppose, setup slack is positive.means in your design there is no violation.if slack is negative, there is some violation.
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